The present invention relates to the use of twisted pair connections as communication links driven by transformer couplings, and particularly to the use of phantom circuits formed by pairs of transformers driving pairs of twisted pairs.
A phantom circuit is formed by connections to the centre taps of a pair of transformers at a transmit end, which pair of transformers are linked by respective communication links to a pair of transformers at a receive end, connections to the centre taps of the transformers at the receive end forming the other end of the phantom circuit. The communication links between the two transformers of the transmit end and the two transformers of the receive end form two high speed communication links and the phantom circuit provides a further low speed communication link. Thus advantageously phantom circuits provide an additional communications link without the provision of additional communications link circuitry.
Typically the communication links formed by the respective pairs of transformers will transmit high speed data, typically between computers. The phantom circuit cannot support high speed communication such as that between computers, but can advantageously be used in accordance with the present invention to distribute power from a transmit end to a receive end; the phantom circuit being used to supply power to devices to which the high speed communication links are connected.
Thus according to the present invention there is provided a communication system comprising:
a first high speed link having a first transformer interface at a transmit end and a second transformer interface at a receive end;
a second high speed link having a third transformer interface at a transmit end and a fourth transformer interface at a receive end;
a low speed link comprising a phantom circuit formed by the first to fourth transformers, the transmit end of the low speed link being formed by connections to the centre taps of the first and third transformers and the receive end of the low speed link being formed by connections to the centre taps of the second and fourth transformers;
wherein the transmit end of the low speed link is connected to a power supply and at least one of the high speed links is connected to a device at the receive end for receiving signals from the respective high speed link, the receive end of the low speed link providing power to the device from the power supply.
Preferably one of the high speed links transmits a serial data signal, and the other high speed link transmits a strobe signal having transitions only at bit boundaries of the data signal where there are no transitions, thus forming a data-strobe communication link as disclosed in earlier European Patent Application Publication No. 0458648.
In addition to the distribution of power, the phantom circuit may be used to transmit low speed signals. The phantom circuit may also be used to distribute a global signalling clock. The global signalling clock may be implemented by providing a switch on the transmit side of the phantom circuit which switches the power supply for transmission in and out of the phantom circuit.
The phantom circuits may also be used to distribute power to remote destinations where there are no devices for receiving high speed communication signals.
The present invention also relates to a communication system in which a variable frequency clock is used in the transmission circuit. The invention is particularly, but not exclusively, concerned with the use of spread spectrum clocks in the transmission circuits of communications systems.
For communication networks, particularly those implemented in the home, there is a need to minimise electromagnetic radiation. The use of spread spectrum clocks reduces the peaks of electromagnetic radiation at harmonics of the clock frequency, and thus it would be advantageous to employ a variable frequency clock such as a spread spectrum clock in any communication system utilising a high speed network, particularly in the home.
Thus according to the present invention there is provided a communications interface comprising output circuitry for providing a data signal to be transmitted under the control of a transmit clock signal, the frequency of the transmit clock signal being continuously variable.
The data-strobe link can cope very well with changing clock frequency, whereas typical PLL clock recovery circuits may have more difficulty in tracking the viable frequency clock.
When using a variable frequency clock in a transmission circuit, further problems arise in attempting to recover the clock at the receive end. European Patent Application Publication No. 0458648 describes an encoding scheme where data is transmitted on one serial link, and on a parallel serial link a strobe signal is transmitted which has transitions only at bit boundaries of the data signal where there is no transition. Such an encoding scheme advantageously allows the transmit clock to be simply recovered at the receive end, and therefore such a communication system can be advantageously used with the variable clock.
Thus according to the present invention there is additionally provided a communications interface comprising:
output circuitry for providing two parallel outputs, one in the form of a data signal and one in the form of a strobe signal and including strobe generation circuitry, wherein the data signal comprises a serial bit pattern and the strobe generation circuitry generates the strobe signal such that the strobe signal has signal transitions only at bit boundaries where there is no transition on the data signal, the strobe generation circuitry being controlled by a clock signal such that for each clock pulse where there is no signal transition in the data signal a signal transition is generated in the strobe signal, the frequency of the clock signal being continuously variable; and
input circuitry having two inputs for receiving data and strobe signals, and including an exclusive-or circuit for receiving the data and strobe signals and generating a receive clock on the output thereof, the receive clock being generated with clock signal transitions having a timing matching that at which the strobe and data signals were transmitted.
The present invention also relates to receive circuitry for use in a communications system utilising data-strobe encoding in which the receiver is insensitive to which of the parallel signal lines the data signal is on. Data strobe encoding is described in earlier European Patent Application Publication No. 0458648.
In the data strobe encoding scheme, a data signal is transmitted on a serial data line, and a strobe signal transmitted on a serial strobe line parallel to the data line, the strobe signal having transitions only at bit boundaries of the data signal where there are no transitions. On the receive side, the transmit clock can be readily recovered by exclusive-ORing both the data and strobe signals.
According to the present invention there is provided data receiving circuitry comprising:
input circuitry having two inputs, one input for receiving a data signal and the other input for receiving a strobe signal, the strobe signal being parallel to the data signal and having signal transitions only at bit boundaries where there is no transition on the data signal;
an exclusive-or gate, having inputs connected to the two inputs, and generating a receive clock on the output thereof;
detection circuitry having two inputs coupled to the respective two inputs of the input circuitry and for detecting an expected bit sequence associated with the data signal on one of said two inputs;
output circuitry for outputting the data signal under the control of the receive clock; and
selection circuitry for connecting the one of said inputs on which said sequence is detected to the output circuit.
The present invention further relates to a communications system code which utilises transformer couplings to communication links, and particularly to such a code employing a data strobe encoding scheme.
The data strobe encoding scheme is described in European Patent Application Publication No. 0458648. A serial data signal is transmitted on one line, and a serial strobe link signal transmitted parallel on a second line. The strobe signal has transmissions only at bit boundaries of the data signal at which there are no transitions on the data signal.
For certain applications, and particularly for high speed networks in the home, it is desirable to employ a communications system in which devices are transformer coupled to allow isolation. If transformer coupling is being used to interface to communication links, then the signals being transmitted must be dc balanced. However the data strobe communication code described in European Patent Application Publication No. 0458648 is not a dc balanced code.
Furthermore, for high speed networks and also particularly for applications of high speed networks in the home, it is desirable to use a simple encoding and decoding technique to minimise cost.
It is also desirable, particularly for applications of communication systems in the home, to minimise any electromagnetic radiation associated with the coding scheme.
A number of codes are in existence which have some of the desirable properties required for a high speed network in the home. The DS link code, mentioned hereinabove, is exceptionally simple to encode and decode, it uses two signal wires such that data is transmitted without further encoding on the data signal wire, and the strobe signal wire changes its state whenever the data signal wire does not change at bit boundaries. This also has the advantage that clock recovery is a simple exclusive ORing of the data and strobe signals at the receive end, so there is no need for a PLL or a DLL to recover the received clock. However there is nothing inherent in the DS link code which minimises electromagnetic radiation. A further major disadvantage of the DS link code is that it is not dc balanced and is therefore not suitable for transformer coupling.
There are many dc balanced codes and particularly pseudo-ternary codes which have the advantage that, in the quiescent state, there is no current flow in the coupling transformer. Regulated mark inversion, described in Electronic Letters, Nov. 9th 1995, pp. 1996-1997, is a simple pseudo-ternary code in which a 1 is always represented as a xe2x88x921 or +1, and a 0 is always represented as 0. Thus the decoded data is always a simple rectification of the received signal. The regulated mark inversion code has an improved emission spectrum over many other codes, with reduced components at both high frequencies and low frequencies, and only increased components between one tenth and one hundredth of the bit rate. The regulated mark inversion code can be controlled to limit the run length of consecutive 1""s, such that there are never more consecutive 1""s than the maximum disparity permitted by the particular implementation of the regulated mark inversion code. By ensuring that transitions in the regulated mark inversion code are always between xe2x88x921 and 0, 0 and xe2x88x921, +1 and 0, or 0 and +1, and never between xe2x88x921 and +1 or +1 and xe2x88x921, then the frequency of the electromagnetic radiation can be further reduced. This also further simplifies the receiver, because it only has to see a transition, rather than discriminate between two different size of transitions of a ternary code. However, the regulated mark inversion code does not allow for simplified clock recovery at the receive end.
Neither the data strobe link code itself, nor the regulated mark inversion code, is particularly suitable for optical fibre implementation. Codes that are much more suitable include the serial HIPPI code and the HS-LINK code of IEEE 1355. These are binary codes which maintain dc balance by inverting the data if necessary to reduce the running digital sum of the code. Each code word includes an inversion flag to indicate inversion, and because the inversion has particular significance, it is normally accompanied by a parity bit which covers parity of both the data and the flag.
Thus it is an object of the present invention to provide a communication code which enables simple clock recovery at the receive end, is dc balanced, minimises electromagnetic radiation, and is suitable for transformer coupling.
Thus according to the present invention there is provided a method of establishing parallel data and strobe signal communication paths having dc balanced data and strobe signals on each path, comprising:
outputting a binary data signal;
generating and outputting a binary strobe signal, parallel to the binary data signal, having signal transitions only at bit boundaries where there is no transition on the parallel binary data signal; and
encoding the binary data signal and the binary strobe signal into respective ternary dc balanced signals for transmission.
Preferably the step of encoding the binary data signal and the binary strobe signal into respective ternary dc balanced signals encodes such signals such that only single level logic transitions are permitted between successive trits of the ternary signals.
Preferably the encoding step comprises the steps of, for each of the data and strobe signal:
calculating the running digital sum of the ternary signal;
transmitting next binary 1 as ternary xe2x88x921 if the running digital sum is positive and at least two 0""s have been transmitted since the last ternary +1;
transmitting the next binary 1 as ternary +1 if the running digital sum is negative and at least two 0""s have been transmitted since the last ternary xe2x88x921;
transmitting at least two successive binary 1""s as ternary xe2x88x921""s if the running digital sum is positive and the at least two binary 1""s follow any number of 0""s;
transmitting at least two successive binary 1""s as ternary +1""s if the running digital sum is negative and the at least two binary 1""s follow any number of 0""s; and
otherwise reversing the polarity of each ternary 1 each time a run of at least one 0 occurs.
The present invention also provides data transmission circuitry comprising:
input circuitry for receiving a binary data signal;
strobe generation circuitry for generating a binary strobe signal, parallel to the binary data signal, and having signal transitions only at bit boundaries where there is no transition on the parallel binary data signal;
encoding circuitry for encoding the binary data and strobe signals into respective ternary dc balanced signals; and output circuitry for transmitting the ternary encoded data and strobe signals.
According to another aspect of the invention there is provided a method of decoding a ternary data signal and a ternary strobe signal, the strobe signal being parallel to the data signal and having signal transitions only at trit boundaries of the data signal where there is no transition, the method comprising:
rectifying the ternary data and strobe signals to generate binary data and strobe signals;
exclusive-ORing the data and strobe signals to generate a receive clock; and
outputting the rectified data signals under the control of the receive clock.
This aspect of the invention also provides data receiving circuitry comprising:
input circuitry for receiving a ternary data signal and a ternary strobe signal, the strobe signal being parallel to the data signal and having signal transitions only at bit boundaries where there is no transition on the data signal;
rectification circuitry for rectifying the ternary data and strobe signals and generating binary data and strobe signals;
an exclusive-OR gate for receiving the data and strobe signals and generating the receive clock at its output; and
output circuitry for outputting the binary data signal under the control of the receive clock.